Recently, PWM (pulse width modulation) has been widely used for controlling switching power supplies, for driving motors and for driving inverters for fluorescent lamps. In association with this, PWM control circuits that exhibit excellent performance, are small in size, are manufactured at reduced cost, are very reliable and consume less electric power, are highly desirable. To meet these conditions, there is an increased need for power IC's, in which are integrated power semiconductor devices exhibiting a high breakdown voltage. Since the power IC's drive the transformer in a power supply of 100 V or 200 V, it is highly desirable for the semiconductor devices in the power IC to exhibit a breakdown voltage of 700 V. To integrate the semiconductor devices easily with their control means, it is necessary to employ lateral semiconductor devices, the substrate and the drift region of which are highly resistive (lightly doped), as disclosed in The Institute of Electronic Engineers of Japan, EDD-93-21, 21-29 (1993) and U.S. Pat. No. 5,452,370.
FIG. 21 is a cross-sectional view of a conventional semiconductor device exhibiting a high breakdown voltage. Referring to FIG. 21, an n-type well region 172 is formed in a p-type substrate 171 with high resistivity of around 150 ohm-cm. A p-type base region 173 is formed in n-type well region 172. The surface impurity concentration (hereinafter referred to as the “surface concentration”) in n-type well region 172 is 3×1016 cm−3, and the diffusion depth of n-type well region 172 is 6 micrometers. The surface concentration in p-type base region 173 is 3×1016 cm−3, and the diffusion depth of p-type base region 173 is 2 micrometers. The surface concentration of the p-type base region determines the threshold voltage of the power MOSFET.
A p-type diffusion region 179, which works as a p-type offset region, is formed in the surface portion of an n-type drift region (Ld section). The p-type diffusion region 179 is 1 micrometer in depth. The surface concentration of p-type diffusion region 179 is 5×1016 cm−3. Then, an insulation film 180, such as a LOCOS film made by thermal oxidation, is formed on p-type diffusion region 179. Insulation film 180 is 0.6 micrometer in thickness. An n-type source region 175 is in the surface portion of p-type base region 173. An n-type drain region 174 is in the surface portion of n-type well region 172. The n-type source region 175 and n-type drain region 174 are spaced apart from each other with p-type diffusion region 179 interposed therebetween. A polysilicon gate electrode 177 is formed on the extended portion of p-type base region 173 extended between n-type source region 175 and n-type well region 172 with a gate oxide film 183 of 25 nm in thickness interposed therebetween. Not shown are n+-type contact regions, 0.2 micrometer in diffusion depth, which are formed in n-type source region 175 and n-type drain region 174. The surface concentration of the n+-type contact region is 1×1020 cm−3. A p+-type contact region 176 is formed in the surface portion of p-type base region 173. The surface concentration of p+-type contact region 176 is 5×1019 cm−3. The diffusion depth of p+-type contact region 176 is 0.5 micrometer. A interlayer insulation film (not shown) is formed. Contact holes are bored through the interlayer insulation film. A source electrode 181 and a drain electrode 182 are formed. Insulation film 180 is extended onto n-type well region 172, and gate electrode 177 is extended onto the extended portion of insulation film 180. In this structure, the total donor amount in n-type well region 172 below p-type diffusion region 179 is 1×1012 cm−2. A high breakdown voltage is obtained by optimizing the total donor amount in n-type well region 172, the impurity concentration in p-type diffusion region 179, and the width Ld of the n-type drift region. The structure is effective to reduce the on-resistance by increasing the impurity concentration in n-type well region 172, while optimizing the respective impurity concentrations in p-type diffusion region 179 and n-type well region 172 independently.
The conventional steps for forming p-type diffusion region 179 will be briefly described below. FIG. 22(a) is a cross-sectional view illustrating the conventional ion implantation step for forming a p-type impurity diffusion region. FIG. 22(b) is a cross-sectional view for explaining the conventional thermal diffusion step for forming the p-type impurity diffusion region.
Referring to FIG. 22(a), a photoresist 52 is formed on an n-type silicon substrate 51. A photomask (not shown) is positioned on photoresist 52. Photoresist 52 is patterned through this photomask to obtain a mask having an opening, through which ions are implanted. Then boron ion irradiation 55 is performed over the entire surface of silicon substrate 51. Boron ions 54 are implanted through the opening of photoresist 52 into a diffusion region 53. Referring to FIG. 22(b), photoresist 52 is removed. The implanted boron ions are activated thermally and diffused thermally into silicon substrate 51, resulting in a p-type region 56.
Alternatively, an SiO2 film may be used as a mask for the ion implantation. In that case, a sheet of photomask, which is a sheet of glass patterned with emulsion or chromium, is prepared to form a mask for ion implantation.
FIG. 23 is a cross-sectional view of a conventional lateral power MOSFET exhibiting a high breakdown voltage and including the impurity diffusion region described with reference to FIGS. 22(a) and 22(b). The lateral power MOSFET of FIG. 23 exhibits a breakdown voltage of 700 V or higher. When a gate signal of +5 V is applied to a gate electrode 608, a channel is created in a p-type base region 603 beneath a gate electrode. Electrons flow from an n-type source region 604 to an n-type drift region (n-type substrate 601) via the channel. The electrons are absorbed into an n-type drain region 605, resulting in an ON-state of the device. When the gate signal is removed, a reverse bias voltage is applied across the pn-junction plane between p-type base region 603 and the n-type drift region (n-type silicon substrate 601), and the pn-junction plane between the n-type drift region (n-type silicon substrate 601) and a p-type offset region 602, such that a certain breakdown voltage is secured by the entire structure of the device, In FIG. 23, there are shown a p-type contact region 606, a gate oxide film 607, an insulation film 609, a source electrode 610 and a drain electrode 611.
FIG. 24 shows an electric field strength distribution (a) in the cross-section (b) of the conventional semiconductor device exhibiting a high breakdown voltage shown in FIG. 21. When n-type well region 172 in FIG. 21 is heavily doped to reduce the on-voltage, intensive electric field localization is caused on the side of the source electrode as shown in (a) of FIG. 24. Since p-type diffusion region 179 is extended toward the drain electrode, intensive electric field localization is caused also in the anode side surface as shown in (a) of FIG. 24. Due to the electric field localization described above, the electric field strength EA at location A, or the electric field strength EB at location B on the boundary of the oxide film, exceeds 3×105 V/cm, causing a breakdown at location A or B. The breakdown voltage of the structure is determined by the surface structure, and it is also affected (1) by parasitic charges on the boundary of and in the oxide film and (2) by external parasitic charges on the device surface, making the breakdown voltage unstable. When the device is molded with a resin, more intense electric field localization is caused by the moveable ions in the mold resin, reducing the breakdown voltage in some cases. Since the margin of the implanted ion dose amounts in n-type well region 172 and p-type diffusion region 179 for the breakdown voltage is small, a low breakdown voltage is caused by deviations in the amount of the implanted ion dose.
In view of the foregoing, it is an object of the invention to provide a semiconductor device exhibiting a high breakdown voltage, which is also manufactured at low manufacturing cost. It is another object of the invention to provide a semiconductor device that obviates the problems described above and facilitates stabilizing the high breakdown voltage thereof. It is still another object of the invention to provide a method for manufacturing a semiconductor device exhibiting a high breakdown voltage, specifically a method for forming an impurity diffusion region in the semiconductor device.